1. Field of the Invention
The present invention relates to a technology for separating elements in a method for manufacturing a semiconductor element and, particularly, to the manufacturing method using the Shallow Trench Isolation (STI) technology.
2. Description of Related Art
In recent years, along with the microfabrication of a semiconductor element, the STI technology for forming a trench which is filled with an insulating material has been used as a technology for separating the elements. The conventional STI process flow is explained below with reference to FIGS. 9A to 10B.
After forming a protection oxide film 502 on a substrate 501, a nitride film 503 is formed. Then, a resist pattern (not shown) is formed on the nitride film 503 employing a known lithography technology to form a trench 505 in a region for separating semiconductor elements. By using the resist pattern, the nitride film 503, the protection oxide film 502, and the substrate 501 are etched by dry etching successively to form the trench 505 (FIG. 9A).
After forming the trench, the resist material is removed, and then a thermal oxidation (rounding oxidation) is performed to form a rounding oxide film 506 which is a thermal oxidation film, thereby preventing damages on a silicon surface of an inside of a trench, crystallization defects, and contamination and rounding corners of an upper edge of the trench. Then, the trench inside is filled with a CVD oxide film 507 (FIG. 9B). After that, the CVD oxide film 507 on the nitride film 503 is removed (FIG. 9C).
Next, etching (L) is performed in order to adjust the height of the CVD oxide film inside the trench using hydrofluoric acid, so that a surface of an active region is substantially level with a surface of the element separation region (FIG. 10A). After the etching, the nitride film 503 is removed by using a hot phosphoric acid solution, and the protection oxide film 502 on the silicon substrate 501 is removed by using hydrofluoric acid (FIG. 10B).
Next, a shape abnormality indicated by D1 in FIG. 10A, which is a depression in the CVD oxide film and is called a divot, occurs on an upper edge of the CVD oxide film. The underlayer structure before the formation of the CVD oxide film for filling up the trench includes a step 508 (FIG. 9B) which is defined by the rounding oxide film 506 and the nitride film 503 on the trench upper edge, and the cause of the divot is considered to be a difference in hydrofluoric etching rate which is caused since the material of the CVD oxide film formed on the step is different from that of other regions.
The size of the divot is increased with an increase in total amount of the hydrofluoric acid etching performed after the removal of the nitride film as indicated by D2 in FIG. 10B. The CVD oxide film on the trench upper edge is depressed due to the divot, and the succeeding hydrofluoric acid pretreatment causes a reduction in thickness of the thermal oxidation film (rounding oxide film) at the trench upper edge and an exposure of the trench upper edge. Thus, the divot deteriorates element properties
As a method of reducing the size of the divot, a process flow shown in FIGS. 11A to 12C has been proposed. After forming a trench (FIG. 11A) and a rounding oxide film, a nitride film is subjected to an isotropic etching process, which is sometimes referred to as nitride film recess etching, employing wet or dry etching using hot phosphoric acid or the like, so that the step 509 defined by the rounding oxide film and the nitride film is slid from a position directly above an upper edge of the trench to an inside an active region (FIG. 11B).
The rest of the process (after FIG. 11C) wherein the trench is filled with a CVD oxide film is the same as that of the conventional technology mentioned earlier. By the recession of the nitride film, the position on which the divot has occurred is slid to the active region by the silicon recession amount from the conventional trench upper edge (FIG. 12B), and the size of the divot is reduced in the following hydrofluoric acid etching, thereby preventing the depression in the CVD oxide film at the trench upper edge as shown in FIG. 12C.
However, in the above-mentioned method employing the nitride film recess etching, an accurate controllability on the amount of nitride film recess etching and in-plane and inter-plane uniformity are required. With unstable control, a variation in a nitride film thickness occurs, and such variation is increased after post-treatment CMP to lead to a difficulty in setting an etching amount for adjusting the height of the CVD oxide film inside the trench after CMP.
The present invention has been accomplished in view of the problems detected with the conventional semiconductor element manufacturing methods, and an object thereof is to reduce the occurrence of the divot and to provide a novel and improved semiconductor element manufacturing method which is free from the difficulty in setting the etching amount for adjusting the height of the CVD oxide film inside the trench due to increase of variation in the nitride film thickness.